1. Field of the Invention
The present invention relates to integrated circuits in general and to programmable integrated circuits such as FPGA integrated circuits. More particularly, the present invention relates to isolation schemes to permit partial programming of FPGA integrated circuits controlled by Flash memory cells.
2. The Prior Art
FPGA integrated circuits employing Flash memory cells as the programming mechanism are known in the art. Such integrated circuits employ pass transistor or pass gates controlled by Flash memory cells to implement the programmable connections that define the functions and interconnectivity of the circuits.
In many instances, it would be advantageous to be able to partially program the Flash memory contained in Flash-based FPGA integrated circuits. It is difficult to accomplish this in prior-art Flash-based FPGA integrated circuits because Flash memory erase operations are usually done globally since all memory cells share the same well. Performing partial erase while part of the non-volatile memory is operating is challenging because, among other reasons, sensitivity to substrate noise of the sensing circuitry of the non-volatile memory configuration. In particular, sense amplifiers are susceptible to substrate noise.